June 8 – 12, 2026 | Bologna, Italy
DARE will be present at RISC-V Summit Europe 2026 in Bologna.
Join us at the Barcelona Supercomputing Center RISC-V@BSC booth to meet DARE representatives and learn more about our latest developments in advancing RISC-V for European high-performance computing.
The event also features Bond & Build: Our Journey in Tech, a networking initiative dedicated to supporting and connecting women attending the Summit, hosted by Teresa Cervero.
The Summit officially opens on 9 June with welcome remarks from the organisers, including Nick Kossifidis (FORTH), Teresa Cervero (Barcelona Supercomputing Center – BSC), and Andrea Bartolini (University of Bologna – UNIBO).
Technical Contributions
Tuesday, 9 June
Poster: RISC-V Vector 1.0 Code Generation in MLIR-xDSL, Jie Lei (Universitat Politècnica de València)
11:00 – 11:30 Developer Workshop LIBERO: A Flexible, Lightweight GDB-based Visualization Tool for RISC-V Vector Extensions, by Jakob Schäffeler (TUM)
17:45 Presentation: Heuristic-free System Call Interception on RISC-V, Ottavio Monticelli, Iacopo Colonnelli and Marco Edoardo Santimaria (Università di Torino)
Wednesday, 10 June
Poster: QUICK: QEMU Internal Checkpointing for Gem5, Qi Shao (BSC)
17:30 Presentation: Enabling High-Performance Storage for RISC-V: Porting the Lustre Parallel File System, Dave Cremins (Openchip)
Thursday, 11 June
Poster: Energy-Efficiency Optimization of a RISC-V Floating-Point Unit for HPC-Oriented Architectures, Marco Crisologo (BSC)
DARE Featured Session
A key highlight of the week will take place during the workshop “Advancing RISC-V Adoption in HPC and Cloud Environments”, organised by the RISER project, (FORTH, Manolis Marazakis) on 12 June, 9:30 – 16:00.
As part of the workshop, Teresa Cervero and Paul Carpenter from BSC will present:
09:40–10:30 Exploring Next-Generation Vector Architectures with Hardware-Software Co-Design in the DARE Project
The session will explore DARE’s approach to co-designing hardware and software technologies for future European HPC and AI systems, with a particular focus on advanced vector architectures based on RISC-V technologies.
Don’t miss the opportunity to connect with the community and explore how RISC-V is shaping the future of HPC and cloud technologies in Europe.
Register here.
