The European Processor Initiative (EPI) Co-Design Workshop, held on September 10–11 at FORTH in Heraklion, Greece, gathered leading Centres of Excellence (CoEs), research institutions, HPC companies, and hardware/software experts to strengthen Europe’s technological sovereignty in high-performance computing (HPC).

The workshop focused on the collaborative hardware/software co-design approach, a cornerstone for developing next-generation European processor technologies. Participants shared progress on adapting flagship scientific applications to emerging Arm and RISC-V architectures, integrating advanced memory hierarchies, and exploring innovative hardware paradigms such as chiplets and interposers.

Moderated by Etienne Walter (Eviden) and Manolis Marazakis (FORTH), the two-day event featured two keynotes, 20 technical presentations, and two panel discussions, offering a comprehensive overview of Europe’s ongoing co-design efforts.

A dedicated segment of the workshop addressed Reliability, Availability, and Serviceability (RAS) in large-scale computing. Dimitris Gizopoulos (University of Athens) presented on Silent Data Corruptions (SDCs) — undetected hardware faults that can lead to incorrect computation results. While SDC rates may seem low on individual CPUs (0.3–1 per 1,000), they pose significant risks at hyperscale levels. Mitigating these risks demands a holistic co-design approach encompassing hardware and system layers, built around the principles of Model, Measure, Detect, and Mitigate. His presentation, which also featured the DARE project, highlighted how reliability research aligns with DARE’s objectives to ensure robustness and trustworthiness in future RISC-V–based computing systems.

Dimitris Gizopoulos, University of Athens

Paul Carpenter, Barcelona Supercomputing Center (BSC) presented the Digital Autonomy with RISC-V in Europe (DARE) project. DARE is spearheading efforts to enhance European HPC and AI sovereignty by developing a RISC-V–centric open stack that combines chiplet-based hardware (vector, AI, and general-purpose processors) with full software co-design. Its objectives include creating energy-efficient, exascale-ready silicon, accelerating AI workloads, and enabling next-generation scientific computing through virtual and physical prototyping. The project also explores in-memory computing accelerators to support more reliable and energy-conscious AI operations.

Paul Carpenter, BSC

All workshop materials are available on the EPI Dissemination Repository and on the EPI YouTube channel under the playlist “Co-design Workshop in Heraklion.”