November 12, 2026
DARE partner Axelera AI has unveiled Titania, its third-generation AI inference architecture. Titania was designed in Europe with support from DARE (Digital Autonomy with RISC-V in Europe), the EuroHPC Joint Undertaking initiative.
Titania Chiplet Architecture landscape. Image: © Axelera AI
Titania is a chiplet-based design that pairs Axelera’s Digital In-Memory Computing with programmable RISC-V compute in the same package. It uses LPDDR6 memory instead of HBM, giving 128 GB per package. Its reference server, the AX8, delivers 20 PFLOPS (FP8) and 1 TB of accelerator memory in a standard 4U air-cooled server drawing around 5–6 kW. One Axelera server will hold a 1.6 trillion-parameter model at FP4 with the headroom for KV cache, two fit within a legacy 15 kW rack and five fit within a 30 kW air-cooled rack.
The architecture is built for large-scale inference in enterprises, sovereign clouds, telcos, modular data centres, and AI factories. It aims to deliver HPC-class AI performance without the liquid-cooled racks that top-end GPU systems need, so existing data centres can run advanced AI without being rebuilt.
Axelera reports over $300 million in confirmed commitments for Titania. Production starts in Q3 2027 and deployments are planned through early 2028.
Titania shows DARE’s aim in practice: European-designed, RISC-V-based technology that strengthens Europe’s digital autonomy in HPC and AI and is heading for real industrial deployment.
