HARDWARE – VEC
Vector Accelerator (VEC)
A many-core RISC-V vector chiplet for high-precision HPC and emerging applications that combine HPC and AI.
At a glance
Out-of-order RISC-V core
Superscalar core implementing the RISC-V Vector extension 1.0 (RVV 1.0).
Long-vector unit
Multi-lane vector processing unit with 16 kbit vector length.
Matrix extension for AI
Supports AI workloads on the same chip.
Many-core, multi-chiplet
Many cores per chiplet; several chiplets per package.
HBM memory
High-bandwidth memory for data-intensive workloads.
What we are building
The Vector Accelerator (VEC) is DARE’s RISC-V chiplet for high-precision HPC and emerging HPC-AI convergence applications. It is led by Openchip; Barcelona Supercomputing Center (BSC) leads the VEC pathfinding activities.
Each VEC core combines an out-of-order superscalar RISC-V core with a multi-lane long-vector unit and a matrix extension for AI. Many cores are combined in one chiplet, several chiplets are integrated with HBM memory in a System-in-Package, and the package is mounted on a PCIe card.
From VEC core to PCIe card. Chiplet, package and card are symbolic representations
