Towards RISC-V-based HPC: The Italian Pathfinding Activities in the DARE-SGA1 Project2026-06-05T09:54:48+00:00
Modular Arithmetic Based on Boolean Functions: A Divide and Conquer Approach2026-06-05T09:47:18+00:00
Phoebe: Measuring the Unmeasurable—Demystifying Silent Data Corruptions in AI Accelerators Through Microarchitectural Modeling2026-06-05T09:47:42+00:00
Harpocrates++: Automated Functional Program Generation Against CPU Faults and Silent Data Corruptions2026-06-05T09:48:01+00:00
vACE: Exploring the Design Space of Vector Processing Units for Soft Error Vulnerability2026-06-05T09:48:53+00:00
Sisyphus: Cross-Layer Efficiency Across NVM Technologies in Compute-in-Memory Architectures2026-06-05T09:49:17+00:00
Accurate Analysis of Silent Data Corruptions in Programmable AI Accelerator Microarchitectures2026-06-05T09:49:47+00:00
Evaluating ECC for Cache Reliability Under Multi-Bit Upsets: A Design Space Exploration2026-06-05T09:50:17+00:00
Report on Maturity of LLVM’s Fortran Support2025-11-05T08:35:33+00:00
Resources2025-11-04T14:20:15+00:00
The DARE SGA1 project has received funding from the European High-Performance Computing Joint Undertaking (JU) under grant agreement No 101202459. The JU receives support from the European Union’s Horizon Europe research and innovation programme and Spain, Germany, Czechia, Italy, Netherlands, Belgium, Finland, Greece, Croatia, Portugal, Poland, Sweden, France and Austria. Funded by the European Union. Views and opinions expressed are however those of the author(s) only and do not necessarily reflect those of the European Union or of the granting authority. Neither the European Union nor the granting authority can be held responsible for them.

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