June 14, 2026

DARE took part in RISC-V Summit Europe 2026 in Bologna, joining researchers, technology developers and industry leaders from across Europe to showcase the latest advances in open hardware and RISC-V technologies for high-performance computing (HPC).

Throughout the Summit, DARE representatives welcomed visitors at the Barcelona Supercomputing Center (BSC) RISC-V@BSC booth, where attendees learned about the project’s progress in advancing RISC-V technologies for next-generation European HPC and AI systems. The booth provided an opportunity to engage with researchers, exchange ideas with the RISC-V community and strengthen collaborations across the European ecosystem.

The event also featured Bond & Build: Our Journey in Tech, a networking initiative hosted by Teresa Cervero that brought together and supported women attending the Summit, fostering inclusion and community within the European technology landscape.

The Summit opened with welcome remarks from the organisers, including Nick Kossifidis (FORTH), Teresa Cervero (Barcelona Supercomputing Center – BSC) and Andrea Bartolini (University of Bologna – UNIBO), setting the stage for three days of technical presentations, workshops and networking.

Strong Technical Presence

DARE partners contributed to an extensive technical programme, presenting research across compiler technologies, debugging tools, system software, simulation, storage and energy-efficient processor design.

Highlights included:

  • RISC-V Vector 1.0 Code Generation in MLIR-xDSL, presented as a poster by Jie Lei (Universitat Politècnica de València).
  • LIBERO: A Flexible, Lightweight GDB-based Visualization Tool for RISC-V Vector Extensions, a developer workshop delivered by Jakob Schäffeler (Technical University of Munich).
  • Heuristic-free System Call Interception on RISC-V, presented by Ottavio Monticelli, Iacopo Colonnelli and Marco Edoardo Santimaria (Università di Torino).
  • QUICK: QEMU Internal Checkpointing for Gem5, a poster presented by Qi Shao (BSC).
  • Enabling High-Performance Storage for RISC-V: Porting the Lustre Parallel File System, presented by Dave Cremins (Openchip).
  • Energy-Efficiency Optimization of a RISC-V Floating-Point Unit for HPC-Oriented Architectures, a poster presented by Marco Crisologo (BSC).

Heuristic-free System Call Interception on RISC-V, Ottavio Monticelli (Università di Torino)

Together, these contributions demonstrated the breadth of innovation taking place across the DARE consortium and highlighted ongoing efforts to strengthen the European RISC-V software and hardware ecosystem.

Spotlight on DARE’s Hardware–Software Co-Design

A key highlight of the Summit was DARE’s featured contribution to the RISER workshop, “Advancing RISC-V Adoption in HPC and Cloud Environments”, organised by FORTH.

During the workshop, Teresa Cervero and Paul Carpenter (BSC) presented “Exploring Next-Generation Vector Architectures with Hardware-Software Co-Design in the DARE Project.” The session showcased DARE’s approach to jointly developing hardware and software technologies for future European HPC and AI infrastructures, with a particular focus on advanced RISC-V vector architectures.

“Exploring Next-Generation Vector Architectures with Hardware-Software Co-Design in the DARE Project”, Paul Carpenter (BSC)

The presentation illustrated how co-design can accelerate innovation by aligning processor architectures, compiler technologies, software stacks and application requirements, helping to build a competitive and sustainable European computing ecosystem.

Strengthening Europe’s Open Computing Ecosystem

DARE’s participation at RISC-V Summit Europe 2026 reinforced the project’s commitment to advancing open, high-performance computing technologies and contributing to Europe’s growing RISC-V community. Through technical presentations, collaborative discussions and engagement with researchers and industry partners, the project demonstrated the value of coordinated European research in shaping the next generation of HPC and AI systems.